Gallium Nitride (GaN) Substrates

Gallium Nitride (GaN) Substrates
Gallium nitride substrates are matched in lattice constant and thermal expansion properties for epitaxial growth of doped GaN layers needed for fabrication of GaN-based devices. This eliminates stress and defects induced by growing GaN epi-layers on non-nitride substrates such as sapphire or silicon carbide, which increase device fabrication complexity and cost and compromise device performance. Kyma's high purity GaN substrate allows GaN-based device manufacturers to eliminate processing steps and improve device quality over those grown on other substrates.
Kyma currently offers GaN substrates to fill the needs of many applications. Detailed product descriptions and specification sheets are listed below:

C-Plane, N-Type Gallium Nitride (GaN) Substrates
2" rounds, 18x18mm and 10x10mm squares
Specification sheet
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C-Plane, Semi-Insulating Gallium Nitride (GaN) Substrates
18x18mm and 10x10mm squares
Specification sheet
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Non-polar, N-Type Gallium Nitride (GaN) Substrates
50mm2 and 100mm2 bars
M-plane [1-100], A-plane [11-20]
Other planes available on request
Specification sheet
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Specification Sheet Characterization Methods
Characterization of gallium nitride wafers as shown in our specification sheets is completed using the following methods:
Wafer thickness, Bow and TTV are determined by a Sigmatech thickness mapper for round substrates. Square substrates are measured manually at predetermined points on the wafers.
Wafer orientation is determined by x-ray diffraction
Conductivity is determined by Lehighton (n-type, semi-insulating) and/or Corema measurements (semi-insulating) and/or Hall measurements for our boule recipes, but are not made on all wafers shipped.
Dislocation density is determined via etch pit density measurements followed by AFM and/or micro-cathodoluminescence (Micro-CL), but are not made on all wafers shipped.
Macro defects are on the surface of the wafer and are counted by visual inspection.
Surface roughness information is determined by atomic force microscopy (AFM) for the front surface finish. The typical image size for the measurement is 20x20 microns.

高密度二氧化矽薄膜(High Density Silicon Dioxide Films)

Seramic SI
高密度二氧化矽薄膜(High Density Silicon Dioxide Films)
特點:用浸塗或自旋塗佈提供耐熱絕緣層
電子 – 半導體設計和電容的絕緣層
光學 –玻璃和石英表面的防擴散
說明:
Seramic SI is a -chloroethylsilsesquioxane solution in methoxypropanol.
薄膜特性:
透明
介電常數: 3.2-३.6
折射率:
硬化前-- १.५
硬化後-- 2.1-2.2
溶液性質
固含量 14-16%
密度 0.96 g/cc
黏度 3-5 cSt.
閃點 35°C
儲存: 5°C下密封,6個月. 打開前先加溫到 15°C
注意:
在通風無火源下使用, 避免皮膚和眼睛直接接觸
使用方法:
熱固化型-
用浸塗或自旋塗佈, 溶劑揮發後, 300°C 下加熱 30-60分鐘
自旋塗佈, 塗膜的厚度大約 1500-2000 Å
如果需要更薄, 可以用methoxypropanol 或diglyme 稀釋. 加熱過程有少量的乙稀和鹽酸氣體釋出
UV固化型- -
藉 deep UV (<210nm) 固化. 深紫外線照射區耐溶劑侵蝕, 未曝光區域可用溶劑洗去,
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